The present invention relates generally to multi-processor computer systems. More specifically, the present invention provides techniques for handling arbitrated, fixed, and non-vectored interrupts in systems having a plurality of multi-processor clusters.
In computer systems, and particularly multi-processor computer systems, interrupts are mechanisms that an I/O device or a processor can use to signal another processor. Typically, code corresponding to the interrupt is executed on the targeted processor when the interrupt is received. A common infrastructure for communicating such interrupts employs dedicated wires from each device capable of generating an interrupt to an advanced programmable interrupt controller (APIC) which combines and forwards interrupts to the appropriate devices.
A relatively new approach to the design of multi-processor systems replaces broadcast communication among processors with a point-to-point data transfer mechanism in which the processors communicate similarly to network nodes in a distributed computing system. That is, the processors are interconnected via a plurality of communication links and requests are transferred among the processors over the links according to routing tables associated with each processor. The intent is to increase the amount of information transmitted within a multi-processor platform per unit time. In such systems, the point-to-point infrastructure is employed to communicate interrupts rather than the dedicated infrastructure of earlier systems.
One limitation associated with such an architecture is that the node ID address space associated with the point-to-point infrastructure is fixed, therefore allowing only a limited number of nodes to be interconnected. In addition, the infrastructure is flat, therefore allowing a single level of mapping for address spaces and routing functions. As a result, interrupts are only visible to nodes (e.g., processors) in a single processor cluster defined by the limited node ID space. That is, this architecture does not provide a mechanism by which interrupts may be seen by processors in remote clusters. Therefore, construction of systems based on this architecture which include more than one multi-processor cluster is problematic. It is therefore desirable to provide techniques by which computer systems employing this infrastructure are not so limited.